This invention relates to a method and apparatus for enabling unlimited phase tracking in high speed data synchronisation, for example in telecommunications equipment. The invention relates in particular to a delay locked loop which provides continuous, precise alignment of two signals in excess of one signal period. The invention also relates to a phase shifter circuit which provides phase shifting over more than one signal period.
With increasingly higher data rates becoming common place, particularly in optical systems, it is becoming increasingly difficult to guarantee clock and data alignment. Variations in integrated circuit parameters and printed circuit board signal delays leave a very small time in which clock and data signals may be aligned. These signal delays vary with production tolerances and operating temperatures which can cause significant design problems at high data rates. Frequency and phase locked loops are often used to manage the clock and data alignment and to maintain data integrity throughout the operating range of the high speed data equipment. A delay locked loop, which is a type of phase locked loop, uses a phase detector to generate an error voltage proportional to the phase difference between two input signals. The error voltage is, in turn used to control a phase shifter which adjusts the delay, or phase, of one of the signals to achieve phase alignment of the two signals. Such a circuit allows the phase changes of either signal to be continuously and precisely tracked. The circuit is limited to tracking changes of less than one signal period, that is phase differences in excess of .+-.180.degree. may not be accurately tracked by the phase shifter and can cause the loop to become unstable.
One accepted method of overcoming this instability is to detect the limit of the phase difference and to recentre the phase shifter. Since it is not possible to maintain signal alignment whilst the phase shifter, and thus the loop, is being reset, this results in a temporary loss of alignment. As a consequence, such circuits are unsuitable for use in high speed data equipment where the temporary loss of alignment can severely affect the data integrity of several kilobytes of data.
An alternative approach may be to operate the loop at a submultiple frequency of the signals being tracked. The disadvantage of this approach is that the original frequency needs to be recovered before the output signals can be used. This process introduces further errors and complications into the circuitry.
There is thus a need for an improved phase shifter and delay locked loop which do not suffer from the disadvantages outlined above.
It is an object of the invention to provide a phase shifter which can track phase changes seamlessly, which maintains alignment throughout all phase differences and which does not introduce further complexity or errors.